The present invention relates to the field of integrated circuits; more specifically, it relates to double data rate (DDR) dynamic random access memory (DRAM) burn-in testing.
Two main types of DRAMs are, single data rate (SDR) and a double data rate (DDR). In SDR mode, data comes out of the DRAM on a rising clock edge. In DDR mode, data is delivered externally on both a rising and falling clock edge. Furthermore, DDR architecture requires a two clock internal write latency (the number of clocks of delay from when the write command is issued to the DRAM externally until the column select is activated in the DRAM array), while SDR requires no internal write latency. Insitu burn-in testing of a DRAM in DDR mode, therefore, takes a significantly longer time than in SDR mode and can exceed the retention time specification of the DRAM cell, generating false fails. Current testing methods of dual mode (SDR and DDR) DRAMs therefore rely only on insitu burn-in testing of the DRAM in SDR mode. However, for DRAMs having only DDR mode circuitry, insitu burn-in testing is problematical. Therefore, a method of insitu pattern burn-in testing of DDR mode only DRAMs is required.